View ICS525-02_865964.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

ICS525-01/02/11/12
User Configurable Clock
Description
The ICS525-01/02/11/12 are the most flexible way to generate a high-quality, high-accuracy, high-frequency clock output from an inexpensive crystal or clock input. The user can configure the device to produce nearly any output frequency from any input frequency by grounding or floating the select pins. Neither microcontroller, software, nor device programmer are needed to set the frequency. Using Phase-Locked Loop (PLL) techniques, the device accepts a standard fundamental mode, inexpensive crystal to produce output clocks up to 250 MHz. It can also produce a highly accurate output clock from a given input clock, keeping them frequency locked together. For similar capability with a serial interface, use the ICS307. For simple multipliers to produce common frequencies, refer to the ICS50x family of parts, which are smaller and more cost effective. These products are intended for clock generation. They have low output jitter (variation in the output period), but input to output skew and jitter are not defined nor guaranteed. For applications which require defined input to output timing, use the ICS527-01.
Features
* Packaged as 28-pin SSOP (150 mil body) * Industrial and commercial versions available in Pb
(lead) free package
* User determines the output frequency by setting all * * * * * * * * * * * *
internal dividers Eliminates need for custom oscillators No software needed Online calculator determines register settings Pull-ups on all select inputs Input crystal frequency of 5 - 27 MHz Input clock frequency of 2 - 50 MHz Very low jitter Duty cycle of 45/55 up to 200 MHz Operating voltage of 3.0 V or 5.5 V Ideal for oscillator replacement Industrial temperature version available For Zero Delay, refer to the ICS527
Block Diagram
2 PD X1/ICLK Crystal or clock input Crystal Oscillator X2 Reference Divider Phase Comparator, Charge Pump, and Loop Filter VCO Divider CLK VCO Output Divider REF VDD
Optional crystal capacitors
7 R6:R0
9 V8:V0
2
GND
3 S2:S0
MDS 525-01/02/11/12 Q Integrated Circuit Systems, Inc.
1
525 Race Street, San Jose, CA 95126
Revision 101105 tel (408) 297-1201
www.icst.com
ICS525-01/02/11/12 User Configurable Clock
Pin Assignment
R5 R6 S0 S1 S2 VDD X1/ICLK X2 GND V0 V1 V2 V3 V4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 R4 R3 R2 R1 R0 VDD REF CLK GND PD V8 V7 V6 V5
ICS525-01/-02/-11/-12
Pin Descriptions
Pin Number
1, 2, 24-28 3, 4, 5 6, 23 7 8 9, 20 10 - 18 19 21 22
Pin Name
R5, R6, R0-R4 S0, S1, S2 VDD X1/ICLK X2 GND V0 - V8 PD CLK REF
Pin Type
I(PU) I(PU) Power X1 X2 Power I(PU) Input Output Output
Pin Description
Reference divider word input pins determined by user. Forms a binary number from 0 to 127. Select pins for output divider determined by user. See table on page 3 Connect to VDD. Crystal connection. Connect to a parallel resonant fundamental crystal or input clock. Crystal connection. Connect to a crystal or leave unconnected for clock. Connect to ground. VCO divider word input pins determined by user. Forms a binary number from 0 to 511. Power-down. Active low. Turns off entire chip when low. Clock outputs stop low. Output clock determined by status of R0-R6, V-V8, S0-S2, and input frequency. Reference output. Buffered crystal oscillator (or clock ) output.
KEY: I(PU) = Input with internal pull-up resistor; X1, X2 = crystal connections
MDS 525-01/02/11/12 Q Integrated Circuit Systems, Inc.
2
525 Race Street, San Jose, CA 95126
Revision 101105 tel (408) 297-1201
www.icst.com
ICS525-01/02/11/12 User Configurable Clock
ICS525-01 Output Frequency and Output Divider Table
S2 S1 S0 CLK Output Pin 5 Pin 4 Pin 3 Divider Output Frequency Range (MHz) VDD = 5 V 0 - 70C 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 10 2 8 4 5 7 9 6 3-26 15-160 3.75-40 7.5-80 6-50 4-40 3.3-33.3 5-53 -40 to +85C 3-23 15-140 3.75-36 7.5-72 6-45 4-36 3.3-30 5-47 VDD = 3.3 V 0 - 70C 3-18 15-100 3.75-25 7.5-50 6-34 4-26 3.3-20 5-27 -40 to +85C 3-16 15-90 3.75-22 7.5-45 6-30 4-23 3.3-18 5-24
ICS525-02 Output Frequency and Output Divider Table
S2 S1 S0 CLK Output Pin 5 Pin 4 Pin 3 Divider Output Frequency Range (MHz) VDD = 5 V -40 to +85C 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 6 2 8 4 5 7 1 3 5-67 15-200 3.75-50 7.5-100 6-80 4-57 30-250 10-133 VDD = 3.3 V -40 to +85C 5-40 15-120 3.75-30 7.5-60 6-48 4-34 30-200 10-80
ICS525-11 Output Frequency and Output Divider Table
S2 S1 S0 CLK Output Pin 5 Pin 4 Pin 3 Divider Output Frequency Range (MHz) VDD = 5 V 0 - 70C 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 10 2 8 4 5 7 9 6 0.75-6.5 3.75-40 0.94-10 1.875-20 1.5-12.5 1-10 0.83-8.33 1.25-13.25 -40 to +85C 0.75-5.75 3.75-35 0.94-9 1.875-18 1.5-11.25 1-9 0.83-7.5 1.25-11.75 VDD = 3.3 V 0 - 70C 0.75-4.5 3.75-25 0.94-6.25 1.875-12.5 1.5-8.5 1-6.5 0.83-5 1.25-6.75 -40 to +85C 0.75-4 3.75-22.5 0.94-5.5 1.875-11.25 1.5-7.5 1-5.75 0.83-4.5 1.25-6
MDS 525-01/02/11/12 Q Integrated Circuit Systems, Inc.
3
525 Race Street, San Jose, CA 95126
Revision 101105 tel (408) 297-1201
www.icst.com
ICS525-01/02/11/12 User Configurable Clock
ICS525-12 Output Frequency and Output Divider Table
S2 S1 S0 CLK Output Pin 5 Pin 4 Pin 3 Divider Output Frequency Range (MHz) VDD = 5 V -40 to +85C 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 6 2 8 4 5 7 1 3 1.25-16.75 3.75-50 0.94-12.5 1.875-25 1.5-20 1-14.25 7.5-62.5 2.5-33.25 VDD = 3.3 V -40 to +85C 1.25-10 3.75-30 0.94-7.5 1.875-15 1.5-12 1-8.5 7.5-50 2.5-20
MDS 525-01/02/11/12 Q Integrated Circuit Systems, Inc.
4
525 Race Street, San Jose, CA 95126
Revision 101105 tel (408) 297-1201
www.icst.com
ICS525-01/02/11/12 User Configurable Clock
( VDW + 8 ) ( RDW + 2 ) * OD
External Components/Crystal Selection
Decoupling Capacitors
The ICS525-01/02/11/12 requries two 0.01F decoupling capacitors to be connected between VDD and GND, one on each side of the chip. The capacitor must be connected close to the device to minimize lead inductance.
CLK Frequency = Input Frequency x 2x --------------------------------------------
Where: Reference Divider Word (RDW) = 0 to 127 (0 not permitted for ICS525-01/-11) VCO Divider Word (VDW) = 0 to 511 (0, 1, 2, 3 not permitted for ICS525-01/-11) Output Divider (OD) = values on pages 3-4 Also, the following operating ranges should be observed: 1. The output frequency must be in the ranges listed on pages 3-4. 2. The phase detector frequency must be above 200 kHz.
InputFrequency 200kHz < ---------------------------------------------( RDW + 2 )
External Resistors
A 33 series termination resistor should be used on the CLK and REF pins.
Crystal Load Capacitors
The approximate total on-chip capacitance for a crystal is 16 pF, so a parallel resonant, fundamental mode crystal with this value of load (correlation) capacitance should be used. For crystals with a specified load capacitance greater than 16 pF, crystal capacitors may be connected from each of the pins X1 and X2 to Ground as shown in the block diagram. The value (in pF) of these crystal caps should be (CL -16)*2, where CL is the crystal load capacitance in pF. These external capacitors are only required for applications where the exact frequency is critical. For a clock input, connect to X1 and leave X2 unconnected (no capacitors on either).
Since all of the inputs have pull-up resistors, it is only necessary to ground the pins that need to be set to zero.
Which Part to Use?
The ICS525-01 is the original configurable clock. The ICS525-02 has a higher maximum output grequency and a slightly different set of output dividers. The ICS525-11 has the same divider set as the -01 but is optimized for low frequency operation. The ICS525-12 has the same divider set as the -02 but is optimized for low frequency operation. To determine the best combination of VCO, reference, and output divide, use the ICS525 Calculator on our web site.
Determining the Output Frequency
Users have full control in setting the desired output frequency over the range shown in the tables on pages 3-4. To replace a standard oscillator, users should connect the divider select input pins directly to ground (or VDD, although this is not required because of internal pull-ups) during Printed Circuit Board layout. The ICS525 will automatically produce the correct frequency when all components are soldered. It is also possible to connect the inputs to parallel I/O ports to switch frequencies. By choosing divides carefully, the number of inputs which need to be changed can be minimized. Observe the restrictions on allowed values of VDW and RDW.
Configuration Pin Settings
The output of the ICS525 can be determined by the following simple equation:
MDS 525-01/02/11/12 Q Integrated Circuit Systems, Inc.
5
525 Race Street, San Jose, CA 95126
Revision 101105 tel (408) 297-1201
www.icst.com
ICS525-01/02/11/12 User Configurable Clock
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS525-01/02/11/12. These ratings, which are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range.
Item
Supply Voltage, VDD All Inputs and Outputs Ambient Operating Temperature, Commercial Ambient Operating Temperature, Industrial Storage Temperature Junction Temperature Soldering Temperature 7V
Rating
-0.5 V to VDD+0.5 V 0 to +70C -40 to +85C -65C to 150C 125C 260C (max. of 10 seconds)
DC Electrical Characteristics
Unless stated otherwise, VDD = 3.3 V
Parameter
Operating Voltage Operating Supply Current
Symbol
VDD IDD
Conditions
60 MHz out, no load, 15 MHz crystal, ICS525-01/02 only 40 MHz out, 15 MHz crystal, ICS525-11/12 only Pin 19 = 0, Note 1
Min.
3.0
Typ.
8
Max.
5.5
Units
V mA
Operating Supply Current
IDD
6
mA
Operating Supply Current, Power-down Input High Voltage Input Low Voltage Input High Voltage, X1/ICLK only Input Low Voltage, X1/ICLK only Output High Voltage Output Low Voltage
IDD VIH VIL VIH VIL VOH VOL
4 2 0.8
A V V V
VDD/2-1
ICLK (pin7) ICLK (pin7) IOH = -12 mA IOL = 12 mA
VDD/2+1
VDD/2 VDD/2
V V
VDD-0.4
0.4
V
MDS 525-01/02/11/12 Q Integrated Circuit Systems, Inc.
6
525 Race Street, San Jose, CA 95126
Revision 101105 tel (408) 297-1201
www.icst.com
ICS525-01/02/11/12 User Configurable Clock
Parameter
Short Circuit Current Input Capacitance On-chip Pull-up Resistor
Symbol
CIN RPU
Conditions
CLK and REF outputs V, R, S pins and pin 19 V, R, S pins and pin 19
Min.
Typ.
55 4 270
Max.
Units
mA pF k
AC Electrical Characteristics
Unless stated otherwise, VDD = 3.3 V
Parameter
Input Frequency Output Clock Rise Time Output Clock Fall Time Output Clock Duty Cycle, OD = 2, 4, 6, 8, or 10 Output Clock Duty Cycle, OD = 3, 5, 7, or 9 Output Clock Duty Cycle, OD = 1 (-02 and -12 only) Power-down Time, PD low to clocks stopped Power-up Time, PD high to clocks stable Absolute Clock Period Jitter, ICS525-01, Note 2 One Sigma Clock Period Jitter, ICS525-01, Note 2 Absolute Clock Period Jitter, ICS525-02, Note 2 One Sigma Clock Period Jitter, ICS525-02, Note 2 Absolute Clock Period Jitter, ICS525-11, Note 2 One Sigma Clock Period Jitter, ICS525-11, Note 2 Absolute Clock Period Jitter, ICS525-12, Note 2 One Sigma Clock Period Jitter, ICS525-12, Note 2
Symbol
FIN
Conditions
Crystal input Clock input 0.8 to 2.0 V 2.0 to 0.8 V At VDD/2 At VDD/2 At VDD/2
Min.
5 2
Typ.
Max.
27 50
Units
MHz MHz ns ns
1 1 45 40 35 49 to 51 55 60 65 50 10
% %
ns ms ps ps ps ps ps ps ps ps
tja tjs tja tjs tja tjs tja tjs
Deviation from mean One Sigma Deviation from mean One Sigma Deviation from mean One Sigma Deviation from mean One Sigma
140 45 85 30 160 40 160 40
MDS 525-01/02/11/12 Q Integrated Circuit Systems, Inc.
7
525 Race Street, San Jose, CA 95126
Revision 101105 tel (408) 297-1201
www.icst.com
ICS525-01/02/11/12 User Configurable Clock
NOTE 1: Phase relationship between input and output can change at power-up. For a fixed phase relationship, see the ICS527. NOTE 2: For 16 MHz, 100 MHz output. Use the -02 for lowest jitter.
Package Outline and Package Dimensions (28-pin SSOP, 150 mil Body)
Package dimensions are kept current with JEDEC Publication No. 95, MO-153
Millimeters
28
Inches* Min Max
Symbol
Min
Max
E1 INDEX AREA
E
12 D
A A1 A2 b C D E E1 e L aaa
1.35 1.75 0.10 0.25 -1.50 0.20 0.30 0.18 0.25 9.80 10.00 5.80 6.20 3.80 4.00 0.635 Basic 0.40 1.27 0 8 -0.10
.053 .069 .0040 .010 -.059 .008 .012 .007 .010 .386 .394 .228 .244 .150 .157 0.025 Basic .016 .050 0 8 -0.004
*For reference only. Controlling dimensions in mm.
A 2 A 1 A
c
-Ce
b SEATING PLANE L
aaa C
MDS 525-01/02/11/12 Q Integrated Circuit Systems, Inc.
8
525 Race Street, San Jose, CA 95126
Revision 101105 tel (408) 297-1201
www.icst.com
ICS525-01/02/11/12 User Configurable Clock
Ordering Information
Part / Order Number
ICS525-01R ICS525-01RT ICS525-01RLF ICS525-01RLFT ICS525-01RI ICS525-01RIT ICS525-01RILF ICS525-01RILFT ICS525R-02I ICS525R-02IT ICS525R-02ILF ICS525R-02ILFT ICS525R-11 ICS525R-11T ICS525R-11LF ICS525R-11LFT ICS525RI-11 ICS525RI-11T ICS525RI-11LF ICS525RI-11LFT ICS525RI-12 ICS525RI-12T ICS525RI-12LF ICS525RI12LFT
Marking
ICS525-01R ICS525-01R ICS525-01RLF ICS525-01RLF ICS525-01RI ICS525-01RI ICS525-01RILF ICS525-01RILF ICS525R-02I ICS525R-02I ICS525R-02ILF ICS525R-02ILF ICS525R-11 ICS525R-11 ICS525R-11LF ICS525R-11LF ICS525RI-11 ICS525RI-11 ICS525RI-11LF ICS525RI-11LF ICS525RI-12 ICS525RI-12 ICS525RI-12LF ICS525RI-12LF
Shipping Packaging
Tubes Tape and Reel Tubes Tape and Reel Tubes Tape and Reel Tubes Tape and Reel Tubes Tape and Reel Tubes Tape and Reel Tubes Tape and Reel Tubes Tape and Reel Tubes Tape and Reel Tubes Tape and Reel Tubes Tape and Reel Tubes Tape and Reel
Package
28-pin SSOP 28-pin SSOP 28-pin SSOP 28-pin SSOP 28-pin SSOP 28-pin SSOP 28-pin SSOP 28-pin SSOP 28-pin SSOP 28-pin SSOP 28-pin SSOP 28-pin SSOP 28-pin SSOP 28-pin SSOP 28-pin SSOP 28-pin SSOP 28-pin SSOP 28-pin SSOP 28-pin SSOP 28-pin SSOP 28-pin SSOP 28-pin SSOP 28-pin SSOP 28-pin SSOP
Temperature
0 to +70C 0 to +70C 0 to +70C 0 to +70C -40 to +85C -40 to +85C -40 to +85C -40 to +85C -40 to +85C -40 to +85C -40 to +85C -40 to +85C 0 to +70C 0 to +70C 0 to +70C 0 to +70C -40 to +85C -40 to +85C -40 to +85C -40 to +85C -40 to +85C -40 to +85C -40 to +85C -40 to +85C
Parts that are ordered with a "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments
MDS 525-01/02/11/12 Q Integrated Circuit Systems, Inc.
9
525 Race Street, San Jose, CA 95126
Revision 101105 tel (408) 297-1201
www.icst.com

▲Up To Search▲

Price & Availability of ICS525-02

	To Download ICS525-02 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .